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Authors
Affiliations
1 Sethu Institute of Technology, Pulloor, Kariapatti, IN
2 VLSI Design Dept., Sethu Institute of Technology, Pulloor, Kariapatti, IN
Source
Networking and Communication Engineering, Vol 6, No 4 (2014), Pagination: 150-155
Abstract
This study presents a low complexity multiplier for elliptic curve cryptography system over the GF (2m). One of the basis of polynomial basis in Galois field is used to design the cryptography system. This paper presents an area-time efficient systolic structure for multiplication to the elliptic curve cryptography (ECC). Elliptic curve cryptography requires smaller key size, high speed and low bandwidth. It is provide the same security level like RSA in public key cryptography. Systolic structures are used to design the proposed multipliers. This proposed multipliers have low hardware requirements and regular structures; and they are suitable for VLSI implementations. The proposed design provides less area-delay and power-delay complexities over the existing designs. This low complexity multiplier based elliptic curve cryptography will be implemented using FPGA device.
Keywords
Galois Field, Polynomial Basis Multiplier, Elliptic Curve Cryptography, Systolic Structure.
